The fastest and easiest way to achieve standards-based on-chip encryption and decryption

• Related Resources Product Sheets Certicom Suite B IP Cores (PDF) Certicom Suite B AES IP Core (PDF) Certicom Suite B Hash IP Core (PDF) Certicom Suite B Public Key IP Core (PDF) Certicom Suite B TRNG IP Core (PDF) White Papers Securing Sensor Networks: Getting it Right from the Start with Public-Key (PDF) Achieving DRM Robustness: Device Security from Silicon to the Application (PDF) Solution Sheets Certicom Security for Silicon Design Protection (PDF) Application Notes Certicom Security for Sensor Networks: enabling device mobility in flexible, ad-hoc sensor networks (PDF) Certicom Security for Sensor Networks: ensuring security in wireless sensor networks (PDF) Ask Our Experts

  Encrypts and/or decrypts AES in 128-bit, 192-bit or 256-bit depths
• Fully compliant with latest FIPS 197 and NIST 800-38A
• Multiple configuration modes available, including:
  
  • Electronic Codebook (ECB)
  • Cipher Block Chaining (CBC)
  • Cipher Feedback (CFB)
  • Output Feedback (OFB)
  • Counter (CTR)
• Optional support for other modes such as GCM, CCM, CCM*, XCBC and more depending on design requirements
• Programmable synchronous interface architecture to external circuitry via the Certicom Peripheral Interface for configuration of data, address and control lines
• Optional DMA engine for bus mastering of data into and out of main memory
• Fully integrates with Certicom Security Builder API
• Up to 40 Gigabits per second throughput for high-performance applications, or cost/power-optimized architecture for constrained applications

Certicom Suite B AES IP Cores include:

• Synthesizable RTL code in VHDL or Verilog with Synopsys Design Compiler compatible timing constraints and synthesis make scripts
• Optional gate-level netlist mapped into standard cell libraries
• Static timing analysis scripts compatible with Synopsys PrimeTime including false and multi-cycle path exceptions
• VHDL or Verilog test bench and test vectors complying with FIPS PUB 197
• VHDL, Verilog or optional C behavioral core model
• Full core documentation and functional specifications
• Software interface specifications for optional Certicom Security Builder API