The fastest and easiest way to integrate standards-based on-chip hash functions

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  Enables hashing acceleration using the Secure Hashing Algorithm-2 (SHA-2) in 256-bit, 384-bit and 512-bit digest sizes; optional support for other digest sizes
• Optional support for SHA-1 or MD5 hash acceleration
• Fully compliant with latest FIPS 180-2 and NIST SHA-2
• Optional keyed-hash message authentication code (HMAC) to enhance security and data integrity with full FIPS 198 compliance
• Configurable in either flow-through or co-processing modes
• Programmable synchronous interface architecture to external circuitry via the Certicom Peripheral Interface for customized configuration of data, address and control lines and ease of integration with bus wrappers and system buses
• Optional DMA engine for bus mastering of data into and out of main memory
• Fully integrates with Certicom Security Builder API
• Up to 40 Gigabit per second SHA-256 throughput for high-performance applications, or cost/power-optimized architecture for constrained applications

Certicom Suite B Hash IP Cores include:

• Synthesizable RTL code in VHDL or Verilog with Synopsys Design Compiler compatible timing constraints and synthesis make scripts
• Optional gate-level netlist mapped into standard cell libraries
• Static timing analysis scripts compatible with Synopsys PrimeTime, including false and multi-cycle path exceptions
• VHDL or Verilog test bench and test vectors complying with FIPS 180-2 and NIST SHA (and FIPS 198 for optionally HMAC-enabled cores)
• VHDL, Verilog, or optional C behavioral core model
• Full core documentation and functional specifications
• Software interface specifications for optional Certicom Security Builder API