The fastest and easiest way to integrate standards-based on-chip robust random number generation

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  Enables random number generation based on design guidelines given in ANSI X9.82 to specific entropy bit per second requirements
• Fully compliant with latest NIST 800-22 and BSI ASI31
• Two 128-bit input registers for customized seed value inputs
• Autonomous health checking function to ensure that entropy guidelines are met during operation, with external reporting signal on error
• Secure mode input selection for additional tamper proofing oriented measures
• Optional synchronized digital input for external analog noise to enhance entropy
• Programmable synchronous interface architecture to external circuitry via the Certicom Peripheral Interface for customized configuration of data, address and control lines and ease of integration with bus wrappers and system buses
• Optional DMA engine for bus mastering of data into and out of main memory
• Fully integrates with Certicom Security Builder API
• Up to 1 Gigabit per second random number throughput for high-performance applications, or cost/power-optimized architecture for constrained applications

Certicom Suite B TRNG IP Cores include:

• Synthesizable RTL code in VHDL or Verilog with Synopsys Design Compiler compatible timing constraints and synthesis make scripts
• Optional gate-level netlist mapped into standard cell libraries
• Custom design assistance for physical implementation in an ASIC or FPGA to ensure security and entropy
• Static timing analysis scripts compatible with Synopsys PrimeTime including false and multi-cycle path exceptions
• VHDL, Verilog or optional C behavioral core model
• Custom testing assistance and guidance using NIST random number testing
• Full core documentation and functional specifications
• Software interface specifications for optional Certicom Security Builder API